[Libre-soc-dev] synchronised incremental SV development planning
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Mar 11 21:44:12 GMT 2021
latest fun and games: LD/ST when RA==0 of course needs to know if the
*full* 7 bit is zero / nonzero or not. sigh.
i added decoding/recognition of LD/ST immediates to SVP64Asm successfully,
not the modes yet though. these are different from non-LDST in that
mapreduce is not supported and unit/elstride can be specified.
that allowed me to test sv.stw and i ran smack into RA==0 only testing 5
bits not 7.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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