[Libre-soc-dev] scalar instructions and SVP64
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Mar 11 11:21:06 GMT 2021
so let's go through what is needed to implement this idea.
* first, we would need everyone to stop what they are doing. that
includes world-wide IBM personnel whom Ganesan very kindly notified,
because the specification is now declared "invalid", also Paul who is
on holiday needs to be notified to stop looking at it.
* second the specification needs to be updated. this will require a
minimum 3 weeks possibly 4 involving discussion of whether it's
appropriate, because some of the RM-NN-NNNN combinations are not going
to be possible.
* third, we need to start again with sv_analysis.py. this will be 2
weeks of comprehensive detailed study of the entire v3.0B scalar ISA
to ensure that each instruction fits with the proposed change, and
approximately one week of implementation time.
* then the SVP64Asm class needs to be changed. 2-3 days
* then the SVP64RM class needs to be changed and associated
power_enum.py constants updated. about 2-3 days.
* then PowerDecoder2 needs to be changed. another week.
you get the idea.
1) do we have time to do that right now? answer: no
2) do we have the funding to do that right now? answer: no
3) what would be the impact of the above delays our completion
schedules? answer: really bad.
you get the general idea?
if you were talking about a small incremental non-disruptive change, i
would not have any difficulty with this. however the combinations of
they include MASK_SRC in two of them which takes up some of the bits.
this makes it basically flat-out impossible to do what you propose
without a massive disruptive rewrite.
can you please.
document the idea, raise a bugreport and then please,
help with implementation.
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