[Libre-soc-dev] Luke: jtag testing

Cole Poirier colepoirier at gmail.com
Mon Mar 1 19:48:39 GMT 2021

On Monday, March 1, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> > jtag setup
> > (https://bugs.libre-soc.org/show_bug.cgi?id=517)

> got it.  the FPGA and ASIC variant is near-identical, it should be
> clear to substitute "FPGA" for "sim.py".  also there are soc.debug
> utils such as this
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/
> debug/firmware_upload.py;hb=HEAD

Great thank you! Before I proceed to jtag testing can you please review and
mark the above jtag setup wiki page bug as resolved if you are satisfied
that the instructions there will not lead to the fpga shorting and
releasing it’s magic computer gas ;)


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