[Libre-soc-dev] Questions about the logos.

[Jean-Paul Chaput]

Just becuase I like nice things, should it be possible to
reduce the size of the "pixel" nazca uses so the logos are
less pixelated? Drawback it that it increases a hundredfold
the numbers of "pixels"...

On Tue, 2021-06-15 at 13:29 +0200, Staf Verhaegen (FibraServi) wrote:
> On 15/06/2021 13:01, Jean-Paul Chaput wrote:
> > On Tue, 2021-06-15 at 11:05 +0100, Luke Kenneth Casson Leighton wrote:
> > > ---
> > > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> > > 
> > > 
> > > On Tue, Jun 15, 2021 at 10:50 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> > > wrote:
> > > 
> > > > Hello Staf,
> > > > 
> > > > As said in the title, I have some questions about including
> > > > the logo:
> > > > 
> > > > 1. The GDS do not contains the logo drawn in the top metal layer,
> > > >     but also all the other metals. I assume it is for density reasons.
> 
> For packaging it is OK to only have logo on top metal layer. I did it on 
> a test chip in all metal layers as I was not routing limited and I did 
> put the logo in a corner. Also if ever a die would be delayered you 
> would still have the logo on each metal layer.
> For density one indeed has to make sure that you don't mess up density. 
> If you put a LOGO layer on top that may block generation of dummies. 
> Structures with LOGO on top (can) have more relaxed DRC rules, if you 
> obey normal DRC rules LOGO layer can be left of.
> > > > 
> > > > 2. In additions to those layers, there is a layer Id 150, with
> > > >     DATATYPE 1 to 6. What are they for? I
> > > 
> > > blockage, i presume?  which layer number is that supposed to be?
> > 
> >    Could not tell you which number it is (NDA :-( ), but I have it
> >    and it is not 150...
> 
> It are kind of blockage layers. But these are the layers to block dummy 
> fill on layer metal1 - metal6.
> > 
> > 
> > > f they need to be included,
> > > >     we must create an associated basic layers in techno.py.
> > > > 
> > > > 3. Where do I put the logos on the chip.
> > > 
> > > bottom left
> > > 
> > > They are all around 150um
> > > >     wide, and that do not fit in the spare triangular area in the
> > > >     pads corners.
> > > > 
> > > 
> > > they need to be actually visible under a microscope for TSMC's
> > > people to get the orientation correct - by hand - when putting into
> > > the package.
> > 
> >    We can assume that, as they need to see the bounding area of the
> >    pads, a size close to it is big enough. So, one square logo of
> >    50nm side would perfectly fit.
> 
> Actually I think the software generates figure with pixels of 1um square 
> and then instantiates the top with a magnification to make it (and the 
> pixels) smaller. The LOGOs should be able to fit in the corners, one 
> could also spread the logo over different corners. One should not have 
> to increase the die size because of adding the logos. I also think a 
> logo of 50um square should be OK.
> 
> greets,
> Staf.
> 
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