[Libre-soc-dev] IIT Roorkee 2021 OpenPOWER Workshop,
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Jul 20 09:37:20 BST 2021
On Tue, Jul 20, 2021 at 12:40 AM Richard Wilbur
<richard.wilbur at gmail.com> wrote:
> Regarding cost, is there any reason to believe we would need to use a different process or foundry for the RAM chip? If the same geometry will suffice, we could very likely make a RAM chip for less than the processor because the package should be cheaper—far fewer pins since we’d be using a serial interface.
in 180/130 nm we'd be better off doing HyperRAM (Octa-SPI).
Multi gigabit SERDES are analog and an entire area of research in
their own right.
also Lauri is correct on two counts: (a) the size is massive to
achieve the density and (b) DRAM manufacturers actually vary the
geometry to suit the ASIC. 62.5 nm, 26.983 nm because they get better
yields and the entire Fab is dedicated to mass-producing nothing but
those wafers, they can do it.
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