[Libre-soc-dev] IIT Roorkee 2021 OpenPOWER Workshop,

Richard Wilbur richard.wilbur at gmail.com
Tue Jul 20 00:40:16 BST 2021

> On Jul 16, 2021, at 22:43, Lauri Kasanen <cand at gmx.com> wrote:
>> On Fri, 16 Jul 2021 10:54:43 -0600
>> Richard Wilbur <richard.wilbur at gmail.com> wrote:
>> I wonder whether we could get an OMI-lite version of the spec. which could still replace our DDR phy, et cetera?
> Businesswise a custom memory standard will not fly. Even if you're only
> making 800Mhz 180nm RAM, it's going to be expensive as hell, limited
> volume, and made only by you. The market will say "lol no".

I think you are correct.  Since the market will laugh at anyone until they dominate the current leader, my goal is to provide an alternative with equal or superior capability and the freedom of libre licenses.  In that I believe my goals align with those of the libre-soc project.

Regarding cost, is there any reason to believe we would need to use a different process or foundry for the RAM chip?  If the same geometry will suffice, we could very likely make a RAM chip for less than the processor because the package should be cheaper—far fewer pins since we’d be using a serial interface.

The same criticism could be leveled against the processor we are working on but our target audience is not initially the general market.  We are courting first the folks who care about freedom and are willing to pay a premium for what they care about.

> RAM is only cheap because of the vast volumes. Even the OMI RAM is
> going to be expensive, made only at a single place, hard to order...
> And that's with IBM's order volumes.

I agree.  The advantage of OMI technically is that the capability for easy expansion, high bandwidth, and low latency significantly outstrips all the alternatives.[*]  Hence to maximize the system capabilities for a system with a processor that offers OMI, the integrator will be willing to pay a premium and endure some acquisition headaches.

The chip area required to implement the processor side of OMI is 3.5x smaller than that for DDR4.  The signaling is 16 serial differential simplex lines rather than 64 parallel single-ended duplex lines:
1. a good high frequency design should be easier using differential lines than single-ended lines—differential pairs are great for signal quality and limiting RF radiation and susceptibility, fewer issues with crosstalk,
2. 16 differential pairs will be 32 traces which is half as many wires as the 64 single-ended lines needed for DDR4—less space required on the motherboard, fewer pins required of the processor,
3.  simplex lines don’t incur the latency of driver handoff—bus turn-around time is an issue for duplex signals.


[*]  https://objective-analysis.com/uploads/2021-04-18%20Objective%20Analysis%20White%20Paper%20%E2%80%93%20The%20Future%20of%20Low-Latency%20Memory.pdf

More information about the Libre-soc-dev mailing list