[Libre-soc-dev] [RFC] horizontal SVP64 vectors

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jul 8 20:03:15 BST 2021

i started investigating this, using an MSR bit to indicate "Vertical First".

deep breath: *screeeeeam* :)

all going great (code is messy as hell but otherwise ok, hey what are
unit tests for)

right up until i hit the usual (horizontal) "loop exit conditions".

which of course for scalar destination is an *early end*

now it gets far more complicated, because dststep can advance *beyond
where the scalar op has already been executed*

which brings us on to predication itself, in general, when applied to
Vertical-First, summarises as: Don't Do It!

ok don't use integer predication.  CR predication, which reads one CR
Field per element, is ok.  Int predicates on the other hand, get
quickly out of hand: one instruction in a loop could modify the source
predicate integer used by instructions further down.

even CR-based predication is pretty dicey, i mean, fine as long as
there's no horizontal interaction i.e. all CR bits in all CR elements
are completely independent, but the moment a horizontal CR instruction
is encountered, spangg all bets are off.


that's going to take one hell of a lot of explaining.


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