[Libre-soc-dev] [RFC] horizontal SVP64 vectors

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jul 8 14:09:13 BST 2021

HA! i just realised how Vertical-First (new name, more accurate)
Vectors can be emulated.... in SVP64.

the 1<<r3 predicate option.

basically you cache r3, then set r3=srcstep ANDed with whatever the
*real* predicate bit is, and off you go.

1<<r3 predicate mode set *all the time* is effectively exactly the
same as "Vertical-First".



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