[Libre-soc-dev] [RFC] Matrix and DCT/FFT SVP64 REMAP

[Luke Kenneth Casson Leighton]

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;hb=HEAD

these are now working, manually verified, in the ISACaller simulator.
which is getting hacked to pieces.

i've added in a manual system for setting the REMAP schedules for now:
it needs a FSM HDL variant of the 3D schedule in order to not be
considered a major hack.  the same pathway is to be used, the
"srcsteps" for input regs 1,2,3 and "dststeps" for output regs FRT and
FRS are now decoupled, and ISACaller *manually* sets those up.

in HDL that would be handled by PowerDecoder2.  it will almost
certainly be the case that 2-stage instruction decoding will be
needed, for these.

anyway, it's progress.  tomorrow's continued hacking will involve
adding the FFT scheduler in as well.  then i should at least be able
to do DFT.  DCT is particularly tricky, that comes later.

l.