[Libre-soc-dev] synchronised incremental SV development planning
cestrauss at gmail.com
Fri Jan 22 22:19:26 GMT 2021
On 01/22/2021 09:29, Luke Kenneth Casson Leighton wrote:
> great! i can cover ISACaller. i wonder, hmm, if to keep the
> lock-step and be able to compare, i have a feeling it's going to need
> to also be done as a FSM in ISACaller and power-gem5.
> the reason is that the testing system compares regfiles (and memory)
> based on a single step of running a single instruction. if ISACaller
> does the *entire* loop but TestIssuer does only one, they are now
Would it make sense to compare these only at the end of the vector
instruction, when the loop has finished in both ISACaller and TestIssuer?
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