[Libre-soc-dev] synchronised incremental SV development planning
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Jan 22 12:29:31 GMT 2021
On Fri, Jan 22, 2021 at 10:35 AM Cesar Strauss <cestrauss at gmail.com> wrote:
> On 01/21/2021 10:38, Luke Kenneth Casson Leighton wrote:
> > who would like to do what?
> I can be in charge of adding an increment-based hardware for-loop to the
> TestIssuer FSM.
great! i can cover ISACaller. i wonder, hmm, if to keep the
lock-step and be able to compare, i have a feeling it's going to need
to also be done as a FSM in ISACaller and power-gem5.
the reason is that the testing system compares regfiles (and memory)
based on a single step of running a single instruction. if ISACaller
does the *entire* loop but TestIssuer does only one, they are now
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