[Libre-soc-dev] svp64 context propagation (future)
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jan 3 16:15:40 GMT 2021
whilst waiting until the next svp64 review (wednesday UTC 1800) i've been
busy the past couple of days on some optional (future) features that like
so many things i really want to see in SV at some point. the
implementation priority on this one is low: i just didn't want people to
miss out nor forget it.
alexandre: the bit-stack idea i liked so much i based Context Propagation
on it. some point down the road a 16bit Context can be added. also,
you'll be interested to know: "remap" gets that VL Loop order inversion you
were asking about. and a whole lot more.
jacob: looks like, with Context Propagation, we get something pretty
similar to how SVOrig used to work, except not involving CAMs and not
involving massive setup costs. one thing though, we really need a compact
way to drop 32 bit immediates into SPRs, hi-word and lo-word, i don't know
if this is in v3.1B P64.
the three contexts are:
* svp64 RM
Remap is a bundle of fun (link at the page above). it basically allows up
to three dimensions of reordering of a straight linear Vector. Matrix
Multiply can sometimes be done with a *single* Vector-fma, with the dest
remap going back over the same elements as the two sources are remapped to
column/row ordering as appropriate.
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