[Libre-soc-dev] daily kan-ban update 02jan2021

Cesar Strauss cestrauss at gmail.com
Sat Jan 2 18:30:24 GMT 2021

Last few weeks

* CXXSim update:

nMigen has published a comprehensive list of remaining issues until
CXXSim can be merged. See:


In particular, direct access to memory cells is not yet implemented,
breaking our LDST unit test when run under CXXSim.

VCD output has been improved:

- trace hierarchy now begins at the "top" module, like in PySim
- simulation-only signals are now included
- enum and string traces, on the other hand, are still not implemented

I ran a comprehensive list of our unit tests in both PySim and CXXSim,
and it's looking good for CXXSim.

Unfortunately, our tests are relatively short enough that any speedup is
not observable, given the massive startup time spent compiling the C++
code. Maybe, it would make a difference when booting and running a
complete system.

Recent work on the nMigen CXXSim branch has introduced regressions, so
I'm enjoying some time-off from testing CXXSim, until they are resolved.

* MultiCompUnit unit test update:

Test cases now covers zero_a, immediates, and read and write port masks.

Next week

Continue work on the MultiCompUnit unit tests. Test cases for
shadown/go_die are next, then formal verification.

Future work

* Improve LDSTCompUnit unit tests, add formal verification.
* Continue working on my task list.
* Resume writing the write_gtkw tutorial.



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