[Libre-soc-dev] synchronised incremental SV development planning

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Feb 20 23:35:16 GMT 2021

Rc=1 now works, in ISACaller.  there's still a bit to do:

* disable OE=1 for CRs when SVP64 is enabled, to stop RMW hazards on XER.so
* pick a suitable multiple of 16 location for starting Rc=1 Vectors of CRs.


More information about the Libre-soc-dev mailing list