[Libre-soc-dev] daily kan-ban update 17feb2021

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Feb 17 18:21:39 GMT 2021

On Wednesday, February 17, 2021, Tobias Platen <libre-soc at platen-software.de>
> Verified that running ld/st instructions drives the TestMemory on
wishbone bus
> of the dcache.

that's absolutely fantastic to hear.

> Next step is filling the wishbone memory with a pagetable,

right.  there is a unit test which does this.  let me find it.  cole
implemented it.

right, here it is:

basically that is *two* simulation processes, not the normal "one only".

the 2nd one responds to data requests over wishbone, not from an actual
Memory but instead by "faking" wishbone read requests using a dictionary to
look up requests.

this dictionary can be pre-loaded with the types of pagetable entries you
want, at any address size or location.

the problem with having a large enough nmigen Memory to hold large
addresses is that it will run your system out of physical RAM somewhere
about 15 hours of failing to start.

the only fly in the ointment here is that all the unit tests so far assume
a tiny (64 word) Memory for data and instruction.

setup_memory is what gets called.

the data memory needs to be made optional for the mmu test, replaced with

 sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))

however the moment that is done test_issuer.py will fail so you will need
to create a test_issuer_mmu.py that does things differently.

then as well through the Config class parameters you can safely expand the
data wishbone bus address width to a full 64 bit, safe in the knowledge
that the unit tests won't try to allocate a nmigen Memory of size 2^64.


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