[Libre-soc-dev] first SVP64 Vector Sub-PC for-loop operational in python-based simulator

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Feb 12 15:36:13 GMT 2021


the Finite State Machine which interacts through a new SPR, SVSTATE,
is operational and has 3 out of 8 required unit tests to demonstrate
at least the principle:

* all vector (RT, RA, RB)
* RT=scalar, RA/RB=vector
* RT=vector, RA=scalar, RB=vector

there's 3 registers so there are *eight* actual combinations.  the
number of unit tests - QTY8 multiplied by the number of scalar
instructions - is going to get pretty mental, pretty fast.  still,
hey: omelette, eggs as they say.

predication is going to make it even more fun - here's one of the many
unit tests i added for SV-RV:

on top of that, polymorphic elwidth overrides will also be needed:

the important thing is, here, we've a start, with this (slow)
simulator, and it's functional.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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