[Libre-soc-dev] nmigen 1.0 maintenance

lkcl luke.leighton at gmail.com
Fri Dec 31 18:48:31 GMT 2021

Libre-SOC, one of the largest FOSS users of nmigen, is now the official authorised maintainer of nmigen 1.0, under license from M-Labs, the owner of the nmigen Trademark. nmigen 1.0's new community home is https://gitlab.com/nmigen
and its IRC channel #nmigen is on https://oftc.net

as we have Libre Contributors, in order to remain inclusive of everyone, patches via another git repository or git format-patch (as well as via gitlab) are most welcome and encouraged.

funded kindly by the NLnet Foundation https://nlnet.nl, we have three major enhancements to nmigen 1.0 underway:

* completion of full AST Abstraction, whereby Liskov Substitution Principle of user-derived data types will work correctly with the full nmigen AST and DSL syntax (an analogous principle in python itself is how UserList and UserDict may be used anywhere that list and dict are used)

this will allow innovative third party extensions to nmigen, for example strict data typing, Signal length checking, SIMD and other advanced Signal types, and AST rewriting and enhancement phases, all without requiring user-modification of nmigen itself, whilst still being able to use the existing nmigen syntax.  a SIMD Signal type is currently under extensive development as a proof and demo of the concept.

* addition of a c-based simulation back-end, to join pysim and cxxsim.

the very early prototype with no optimisation at all showed only a 2x slowdown in performance. as more of crtl gets converted to c there is huge room for improvement.

crtl was initially intended solely to provide a means to compile nmigen to c, for standalone external usage completely outside of nmigen and even RTL in general (for example, embedded in the linux kernel).  however the easiest way to test crtl turned out to be to fully complete its integration as an actual simulator target in nmigen.

* the addition of an ASIC Platform.  this will include the ability to automatically integrate with JTAG TAP Boundary Scanning.

building on our initial 180nm IMEC tape-out of July 2021, which was a collaboration between Libre-SOC, Chips4Makers and LIP6, the next ASIC, sponsored by NGI POINTER, will have its JTAG Boundary Scan and IO Pad allocation entirely done from nmigen 1.0.

additional contributions and enhancements always welcome.


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