[Libre-soc-dev] daily kan-ban update 06dec2021
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Dec 6 17:47:28 GMT 2021
On Mon, Dec 6, 2021 at 4:40 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> That looks like a complex change, so first I will be reading what
> happended in the last few hours. Excpect no commit today.
from an API perspective, D-Cache and I-Cache are identical: no change.
however, internally... yeah. i have just identified/noticed for example that
the original, in VHDL, assumes that the tools (Xilinx) will correctly identify
SRAMs as SRAMs simply by marking an array as "distributed".
clearly that is flat-out not happening in yosys / nmigen, therefore those
will have to *explicitly* be given an SRAM. actually, a pair of SRAMs:
one 128-bit wide, the other 92-bit wide (4x 23-bits for the page-table entries)
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