[Libre-soc-dev] daily kan-ban update 03dec2021

lkcl luke.leighton at gmail.com
Fri Dec 3 17:57:33 GMT 2021


fixed test_loadstore1.py and PortInterfaceBase

Tobias: a bit about gates.  gates take time to "settle".  they are transistors, and the voltage change (depending on input) takes time to literally drag itself up or down to a new output, fighting capacitance and resistance, all the way.

this is extremely important to remember when writing HDL and especially simulations.  what you had implemented was:

* clock cycle ticks
* LD is set
* exception occurs (alignment) on a combinatorial
* Settle() was called (which is STILL NOT A CLOCK.TICK)
* the combinatorial output was read noting the
(notice, no clock tick with a "yield" has yet been allowed)
* if exception noted RESET the PortInterface

whilst all the time not ever allowing one single clock tick to occur.

you had also modified PortInterfaceBase to comply with this type of behaviour (not letting a clock tick occur)

you MUST allow room for the hardware to have a FULL clock cycle between changes:

* clock tick
* set the LD
* read the exception flag
* if EXC happened, CLEAR the LD
* allow next operation.


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