[Libre-soc-dev] Reservation Stations confirmed functional in core
luke.leighton at gmail.com
Wed Dec 1 14:44:17 GMT 2021
i just tested increased ReservationStations for the ALU Function Unit and found then fixed a bug where everything was routed to RS number 0.
a short random-instruction-generator creates arbitrary conditions, exercising hazards and overallocation to Function Units.
for the runs done so far everything works great. no guarantee that something will not come up, but it is a big step forward.
ReservationStations are necessary to monitor results as they progress through pipelines and FSMs: they capture operands, register numbers, and associated results, and the reg Hazards associated with the *RS*, not the pipeline (or FSM).
consequently, without ReservationStations, it would not matter how "great" or "fantastic" a pipeline is: only one instruction - ever - would be safe to issue, because its hazards could not be safely monitored. which is clearly ridiculously unacceptable, to only allow one instruction to be running.
it was therefore extremely important to get RSes running and a significant breakthrough that they are.
a next big step will be to reduce the number of clock cycles taken by each ALU: this will require some work on MultiCompUnit which had quite a lot of adjustment to get latency down for running on an ECP5 FPGA.
that introduced a LOT of extraneous clock cycles into the Function Units, which now need to come out.
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