[Libre-soc-dev] [RFC] SVP64 Fail-first Mode "VL inclusive"

lkcl luke.leighton at gmail.com
Sat Aug 28 13:21:45 BST 2021

when working on SV Branches i added a VLSET Mode which truncates the Vector Length at the point where the first CR Test fails, it is effectively identical to Data-dependent Fail-First mode.

however due to the combinations of Great-Big-{AND/OR/NAND/NOR} on the CR tests i realised we also need to be able to either *exclude* or *include* the element being tested from the count that ends up in VL.

once this realisation had sunk in i realised that FFirst could also benefit from the same.

i'm therefore proposing replacing the dz bit in ffirst Rc=0 mode with a VLi bit.

the dz bit is for setting zeroing, which, as i found out from the SV Branches, makes no sense or is incomplete. SV Branches allow a bit to set whether the masked-out element be replaced with a one *or* a zero, but there is nowhere near enough bits available for this additional sophistication in Data-dependent FFirst Mode.

therefore dropping zeroing entirely from ffirst is the more logical choice, i feel, leaving just "skipping" (predicate masking)

thoughts appreciated.


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