[Libre-soc-dev] [RFC] SVP64 Vertical-First Mode, batch processing
luke.leighton at gmail.com
Fri Aug 13 00:22:56 BST 2021
On August 12, 2021 10:14:48 PM UTC, lkcl <luke.leighton at gmail.com> wrote:
>On August 12, 2021 9:37:16 PM UTC, Richard Wilbur
><richard.wilbur at gmail.com> wrote:
>>What if svstep was a state associated with the branch instruction in
>>the Finite State Machine implementing Vertical-First Mode instead of
>>requiring a separate op code, cache space, and a decode slot?
forgot to say, the svstep instruction has a lot more options than sv.bc, and there are not enough bits available spare in 24 bit RM.
also the number of registers that go in and out of bc is already really high:
that's a hell of a lot of registers.
an svstep variant of bc would also need to write to CR. that's *ten* registers, 5 read, 5 write, i don't think any other instruction in the whole of Power ISA has anywhere near that many.
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