[Libre-soc-dev] [RFC] SVP64 Vertical-First Mode, batch processing

Richard Wilbur richard.wilbur at gmail.com
Thu Aug 12 22:37:16 BST 2021

> On Aug 12, 2021, at 06:23, lkcl <luke.leighton at gmail.com> wrote:
> since adding Vertical-First Mode, which is very cool, a lot simpler to add into compilers, and closer to Mitch Alsup's MyISA 66000 Virtual Vectors, the implications have taken some time to sink in.

Very cool indeed.  Sounds like Mitch Alsup’s MyISA 66000 design would be very interesting reading.  Is there public documentation?

It is interesting to me how reminiscent this is of my proposal back in 1988-1990 of a massively serial machine that would decode a section of code and configure connections between functional units and data dependencies.  Then it would go run the code limited only by the timing of data availability.

> VF Mode does *not* increment srcstep/dststep automatically on running an instruction: srcstep/dststep *remain where they are*.  an explicit instruction, svstep, is called to increment src/dststep, then a branch-conditional test of whether VL has been reached, loop back on a BATCH of instructions to do the next element(s).

What if svstep was a state associated with the branch instruction in the Finite State Machine implementing Vertical-First Mode instead of requiring a separate op code, cache space, and a decode slot?  Is svstep used outside of the Vertical-First Mode context?

> i propose this change to:
>     if HorizontalFirst
>          if srcstep < VL
>              srstsep increments
>     else if VerticalFirst
>          if srcstep < *MAXVL*
>               srcstep increments
> questions, comments?

Sounds like a good thing.

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