[Libre-soc-dev] [RFC] SVP64 on branch instructions

lkcl luke.leighton at gmail.com
Sun Aug 8 14:30:53 BST 2021

i've started on the 24 bit RM decoder for BC, combining bits into 2 bit enums with only 3 entries in most cases, quite annoying that, but it is what it is.

svstep for example:
* disabled
* non Rc mode
* Rc mode

and VLSET:
* disabled
* set to VL
* set to VL-1

also with using both elwidth fields there now has to be a MUX on element widths, where the selector of that MUX is dependent on whether the operation is a Branch or not.


fortunately it is local i.e. not dependent on SVSTATE.

i nearly made the mistake of making Branch Conditional dependent on SVSTATE.VerticalFirst Mode, which would have serious adverse consequences for multi-issue decoding.

this is exactly the same reason why i said "Hard No" to the idea of making the decoder critically dependent on when SVSTATE.VL==0

if we were designing something that was specifically intended for non-supercomputer non-multi-issue uses, adding critical dependencies between SVSTATE and the decoder would be perfectly fine.


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