[Libre-soc-dev] [RFC] SVP64 on branch instructions
luke.leighton at gmail.com
Wed Aug 4 12:44:08 BST 2021
On August 4, 2021 10:23:54 AM UTC, lkcl <luke.leighton at gmail.com> wrote:
>On August 3, 2021 6:55:21 PM UTC, Luke Kenneth Casson Leighton
><lkcl at lkcl.net> wrote:
>>... you get the general idea, though: that with sz and SNZ there's a
>>way for predicate masks to interact with the CR Vector, to create
>>Vec-AND and VEC-OR behaviour that, at the same time, still allows CTR
>>the option of counting masked-in elements or all elements.
>we've run out of bits, and i have a feeling that it is more useful to have the option of updating the CR field being tested, taking predicate masks into account, than it is say to keep the Absolute Address functionality of branch.
i just noticed, AA is (bit 30) only in bc:
PO BO BI BD AA LK
0 6 11 16 30 31
whereas for bclr there are bits spare:
PO BO BI /// BH XO LK
0 6 11 16 19 21 31
thus only bc need have altered behaviour from v3.0B
as far as bit definitions are concerned: bclr may set
a new bitfield 16-18.
the reason the branch pseudocode has to change is because the loop on the CR Field Vector must not
run to letting LR or other alterations occur.
i.e. we cannot just use the existing bc pseudocode
and run it in a VL loop.
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