[Libre-soc-dev] Fwd: soclayout problem
Jean-Paul.Chaput at lip6.fr
Tue Apr 27 16:42:20 BST 2021
> the "solution" is to fool yosys to think it is not an external Cell by having unique
> names and unique model names.
> hence the MODEL is spblock_0 spblock_1 spblock_2 spblock_3
One more problem : even if it is flagged as a blackbox, the blif
file will contains a description of the spblock512w64b8w_0.v
telling that "d == q" :
.names d q
Subsequently, the Coriolis blif parser, unifies them and the
"q" port of the spblock512w64b8w_0 disappear. And thus cannot
be connected to the port of the real SRAM block...
You sould modify the Verilog description so the two ports are
not merged, while *not* introducing anything that Yosys may
be tempted to synthetize.
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
/v\ Jean-Paul.Chaput at lip6.fr
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