[Libre-soc-dev] soclayout problem

[Staf Verhaegen]

> 
> hence the MODEL is spblock_0 spblock_1 spblock_2 spblock_3

I think the problem is more related to litex/migen.
Do you need model in the blif ?

In I did `read_verilog top.v` followed `write_blif top.blif`. Attached
are the files.
You see that the io module is used in .subckt but has no model section.
Wouldn't that work ?

greets,
Staf.


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# Generated by Yosys 0.9+4052 (git sha1 4c21eab27, gcc 9.3.0-17ubuntu1~20.04 -fPIC -Os)

.model top
.inputs in
.outputs out1 out2
.names $false
.names $true
1
.names $undef
.subckt io $1=in $2=out1
.subckt io $1=in $2=out2
.end