[Libre-soc-dev] soclayout problem

lkcl luke.leighton at gmail.com
Tue Apr 27 13:01:28 BST 2021

On Tue, Apr 27, 2021 at 12:44 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>

> > you *will* have to do *exactly* what i did in the freepdk45 directory....
> > which (doh) i have not committed the modifications to the build_*.sh
> > scripts to copy over the lower-case spblock512w64b8w_*.v
> >
> > ah, found it:
> >
> https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/build_full_4ksram.sh;hb=HEAD
> >
> > i had only added the required steps to that build script, not to all.
> done
> > now
> > https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=HEAD
>   One correction and one question :
>   Correction: You must also add spblock512w64b8w_X to the list of
>               YOSYS_BLACKBOXES in the Makefile (may be moot, depend
>               on the answer to the question).

ah, yes, sorry.  i have also just added (and pushed) those)

>   Question: Do the four spblock512w64b8w_X, in fact, refer to the
>             same model of spblock_512w64b8w ?

no, they *have* to be named differently.

Because if it is so,
>             they must have the same name as the layout, that is
>             spblock_512w64b8w, so Coriolis can associate netlist
>             and layout.
this is what took me literally an entire day to find the problem.

if they are not completely separate blackboxes, with completely different
names, yosys *WILL NOT* complete.


it will - 100% - without fail - produce an error when trying to create the
BLIF file.

the ONLY solution that i found, after literally an entire day, was to give

it will therefore be necessary to have coriolis2 recognise the five


if you look at this line (274), you will see i have already prepared the
doDesign.py to expect that:


 272             # each sram is named differently (yosys blackbox issue)
 273             for i in range(4):
 274                 sram = DataBase.getDB().getCell( 'spblock512w64b8w_%i'
 275                 if sram:

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