[Libre-soc-dev] VERSA_ECP5 JTAG TAP interface confirmed functional
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Apr 27 00:03:33 BST 2021
JSharpe of #talos-workstation on freenode is going to look at a quote for
us to assemble LFE5G 85k ulx3s with 128 mbyte (1 gbit) SDRAM ICs.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Apr 26, 2021 at 4:24 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> that's an open design.
> found a compatible (TSSOP-66) ASIC with 128 megabytes of RAM. which is
> probably good enough.
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