[Libre-soc-dev] Update on Coriolis & LS180.

lkcl luke.leighton at gmail.com
Mon Apr 26 16:31:47 BST 2021

On Mon, Apr 26, 2021 at 3:05 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>

> On Sun, 2021-04-25 at 18:45 +0100, lkcl wrote:
> >
> > the last time i "fixed" this, it involved actually creating (fake)
> > iopadvss.ap, etc. etc. etc., plus FlexLib dio_x0.ap etc. etc. etc. all
> > of which took some doing, but "worked"....
> >
> > ah hang on, i still have the files.  after copying them into the main
> > subdirectory, i can run "make view".
> >
> > there are zero nets.  *this is even after the routing has completed*
> >
> > likewise, running the command i created, here, *there are no nets*:
> > https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/issues/1
> >
> > you can see, in the program, that it is calling Horizontal.create and
> > Vertical.create then
> > NetExternalComponents.setExternal()...
> >
> > ... it's just that if you then look at the AP file *it has no nets*.
>   This can't work. With FlexLib (TSMC or FreePDK45), the generated
>   layout is in GDS.

okaaaay.  now it is starting to make sense.  that explains why chip_r.gds
exists, where before it did not.

this will make "extraction" interesting (to get the *cts*.vst) files?  that
will still work, right?

    But what we needed was you to supply us with patterns and
>   cocotb setup so that we have a "validation" check.

done already - i just wanted a way to check it *before* you get to use it,
because it literally can take 5-8 weeks to run the compile..

... oh and when it does, it throws a cocotb error.

.... oh and then you correct the error, despite no modifications to the

... cocotb DEMANDS that you recompile the entire lot.  which takes another
5-8 weeks.

    The whole point being that pre-P&R and post-P&R must behave
>   exactly the same. Basically the P&R only insert buffers and
>   diodes. So any problem in post-P&R (which isn't already present
>   in the pre-P&R) would be for me to solve.
>   The ground rule is you cannot mix symbolic and real, it will
>   just don't work.

i was missing that the AP files are meaningless, and everything is in GDS

  The two computer bip & bop at LIP6 have 128Gb of RAM.

two computers is not going to be anything remotely close enough to do the
job and complete in a reasonable time.  you need more like 100 to 200.
this is what we have access to through fed4fire.eu


> But I see the
>   point. I have to check with Marie-Minerve that the extracted netlists,
>   stripped of their parasitics could be write back into VHDL, and so
>   can be published without infringing the NDA.

fantastic.  that would probably work.


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