[Libre-soc-dev] Fwd: Update on Coriolis & LS180.
luke.leighton at gmail.com
Sun Apr 25 13:53:24 BST 2021
---------- Forwarded message ----------
From: *Jean-Paul Chaput* <Jean-Paul.Chaput at lip6.fr>
Date: Sunday, April 25, 2021
Subject: Update on Coriolis & LS180.
To: lkcl <luke.leighton at gmail.com>
Just committed in soclayout the right setup for experiment9/freepdk_c4m45.
Limited to 6 metal layers to emulate TSMC 180nm.
In doDesign, I prefer to express the chip size in term of I/O pad dimensions
(N*PadWidth + 2*PadHeight) for a side and the core size in term of slice
height (so there is no narrow GCell on top or right side).
You should be able to run it now (with pinmux!)
Note that Staf hasn't integrated the display patch for diffusion layers
so the transistors in the standard cells look weird (hidden in fact).
Concerning import of GDS, yes AP (symbolic) has strict limitations and
cannot be mixed with GDS in a design. Either you do everything in
symbolic (AP) or in real (GDS). It is an oversimplification.
But, you can import GDS in Coriollis, but you must be careful not to
do so *across* technologies (imoort 180nm GDS in 45nm for example).
On Sat, 2021-04-24 at 23:03 +0100, lkcl wrote:
> On Saturday, April 24, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> > Running the PnR now... Result in one our...
> btw can it be possible to import GDS for cell libraries?
> staf says ap format has limitations.
> i am still getting that "missing iopadvss" which of course is because no
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
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