[Libre-soc-dev] daily kan-ban update 21apr2021

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Apr 21 20:55:35 BST 2021

On Wed, Apr 21, 2021 at 8:19 PM Tobias Platen
<libre-soc at platen-software.de> wrote:

> today: passing PRTBL to the MMU not regfile (fix bug in test_core.py)


btw yesterday i added an option to test_issuer.py to build with the
MMU and ran it through litex sim.py.  it did actually send out LD/ST
requests to the main wishbone bus.  however it soon started sending
corrupted requests.

i tracked this down by increasing the size of the random dcache.py
tests, and noticed that the addresses that failed had a difference of
256 (0x100000000).

i'll continue to investigate over the next few days: my preferred
approach is to use cocotb simulation of the Microwatt dcache.vhdl, do
gtkwave dumps and other debug logs, and do deep signal-for-signal


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