[Libre-soc-dev] daily kan-ban update 14apr2021

Tobias Platen libre-soc at platen-software.de
Wed Apr 14 20:31:44 BST 2021

On Wed, 2021-04-14 at 20:04 +0100, Luke Kenneth Casson Leighton wrote:
> On Wednesday, April 14, 2021, Tobias Platen <
> libre-soc at platen-software.de>
> wrote:
> > today: working on soc/src/soc/decoder/isa/test_caller_radix.py
> > it fails with a
> > name lwz != NONE - calling ILLEGAL trap, PC: 700
> > see debug.log
> > investigating why it fails
> lwz is in the list
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_enums.py;h=3353d202526ee2a885fd645282ab5b94c7320ef5;hb=291f745751ebe9e3223515fc9520955a0700d740#l216
> usually that error means the instruction cannot be looked up.
> have you run pywriter and accidentally overwritten the ISA mdwn-to-
> python?
> check the contents of soc/decoder/isa/all.py
> l.
all.py looks like that:
# auto-generated by pywriter.py: do not edit or commit
from soc.decoder.isa.caller import ISACaller
from soc.decoder.isa.bcd import bcd
from soc.decoder.isa.branch import branch
from soc.decoder.isa.comparefixed import comparefixed
from soc.decoder.isa.condition import condition
from soc.decoder.isa.fixedarith import fixedarith
from soc.decoder.isa.fixedldstcache import fixedldstcache
from soc.decoder.isa.fixedload import fixedload
from soc.decoder.isa.fixedlogical import fixedlogical
from soc.decoder.isa.fixedshift import fixedshift
from soc.decoder.isa.fixedstore import fixedstore
from soc.decoder.isa.fixedtrap import fixedtrap
from soc.decoder.isa.simplev import simplev
from soc.decoder.isa.sprset import sprset
from soc.decoder.isa.stringldst import stringldst
from soc.decoder.isa.system import system

class ISA(ISACaller, bcd, branch, comparefixed, condition, fixedarith,
fixedldstcache, fixedload, fixedlogical, fixedshift, fixedstore,
fixedtrap, simplev, sprset, stringldst, system):
    def __init__(self, *args, **kwargs):
        super().__init__(*args, **kwargs)
        self.instrs = {

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