[Libre-soc-dev] cxxsim with jtag connections

Richard Wilbur richard.wilbur at gmail.com
Fri Apr 9 22:00:33 BST 2021

> On Apr 9, 2021, at 10:48, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> […]
> though gate-level simulation it is possible to ensure that at every stage
> of transformation the ASIC netlist remains "undamaged".
> we therefore stand a reasonable chance of getting a working ASIC back.


Now the onus is on us to create a great testsuite with good coverage and the depth required to catch errors ideally before we send the design to the foundry—but at least (and most importantly for our reputation) before we send chips to customers!

Three cheers for the test infrastructure!


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