[Libre-soc-dev] WASM flexible-vectors & SimpleV

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Apr 9 10:04:32 BST 2021

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Fri, Apr 9, 2021 at 7:13 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> I mentioned SimpleV on the issue tracker for WASM flexible-vectors -- a WIP
> WASM extension for supporting wide (>128-bit SIMD) vectors.

ah cool

> https://github.com/WebAssembly/flexible-vectors/issues/7#issuecomment-816435127
> https://github.com/WebAssembly/flexible-vectors/issues/12#issuecomment-816427289

it may be worthwhile mentioning that for predicated gather-scatter,
SV's explicit variable-vector-length may be used to guarantee that a
scatter selects a fixed number of (predicated) items in a single
instruction, rather than requiring a loop. illustration:

* mask = 0b100001011 # 4 bits set
* top_bit = 64-CNTTZ(mask) # index of the highest bit of mask
* Vector_Length = top_bit # set VL to cover right up to highest bit
* gather(vector) # guaranteed to do all 4 gathers in one operation

this cannot be done with RISC-V because the RISC-V specification
states that the hardware may set VL to an arbitrary value.  in RISC-V
RVV, the program *requests* a certain VL, but the hardware is
permitted to allocate *less* than the maximum *available* VL
(consequently to guarantee completion, all VL-based operations must be
in a loop construct)  SV *requires* that VL is set to the exact amount
requested, and thus in some cases one inner loop may be removed.

also that twin-predication (source mask separate from dest mask) is
also possible, which gives a form of back-to-back VREDUCE-VEXPAND.
this pattern applies even to GATHER LD/STs


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