[Libre-soc-dev] daily kan-ban update 28sep2020

Cesar Strauss cestrauss at gmail.com
Mon Sep 28 13:31:11 BST 2020

Last week:

* Added a nmutil module to abstract cxxsim use, and select it at run-time.


* Produced a reduced test case for a cxxsim bug.

Until it is fixed in nMigen, avoid using cxxsim to drive, from Python,
any input signal greater than 32 bits. Internal and output signals,
greater than 32 bits, seem to be fine.

Other than that, up to now, cxxsim and pysim do seem to give the exact
same results.

As I noticed, there remains a few rough edges, on the VCD output:

1) enum traces are not supported (gives numerical values instead)
2) extra traces given to the simulator, in the "traces" parameter, are
not supported
3) "top" is not the root of the trace hierarchy
4) some trace names are renamed within the hierarchy.

I'm sure 1 and 2 are known issues, due to the current stage of
development. I'll ask about 3 and 4.

* Wrote formal proof and cover traces for src/soc/experiment/alu_fsm.py

It is challenging to get right, but at least saves the effort of having
to come up with unit tests for all possible combinations of corner cases.

It is likely that I'll start adding these, to complement the unit tests
I work upon, from now on.

This week:

* Add GTKWave documents to src/soc/experiment/alu_hier.py and

* Write a new and improved parallel unit test for

Next (as time permits):

* As soon as the bug in cxxsim is reported to be fixed, test the fix.
Maybe, find new bugs, reduce them, rinse and repeat.

* Write a parallel unit test for src/soc/experiment/compldst_multi.py

* Maybe, add formal proofs to src/soc/experiment/alu_hier.py and

* Add more content to the GTKWave tutorial.

Already done:
1) basic trace display
2) colors
3) styles

Still missing:
1) collapsible trace groups
2) comments in the trace pane
3) hierarchy
4) extra signals
5) string traces



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