[Libre-soc-dev] Quick help
colepoirier at gmail.com
Sun Sep 27 17:26:21 BST 2020
On Fri, Sep 25, 2020 at 1:45 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> yeh this was paainful took me 3 days gtkwave traces.
> i strongly recommed lookigng up "jeanthom nmigen Display" and patching
> nmigen with that, link is in nmutil
> then add sync += Display something look how it is done in dcache.py
> this is.absolutely invaluable to finding out what the hell is going on.
Will do today. I was holding off converting the print statements into
Display until I had the rest of the code roughly in order, at least
enough to pass the assert valid.
> oh btw notice that i chopped 3 bits off the wishbone adr in dcache.py
> the microwatt use of wishbone is NOT compliant with WB4 spec.
> they put the LSBs onto the adr bus that are covered by the sel bits.
Thanks for the reminder, I'll look for it in gitk so I ensure I do it properly.
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