[Libre-soc-dev] change of tapeout date, and roadmap for 180nm ADIC

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Sep 24 16:32:33 BST 2020

On Thu, Sep 24, 2020 at 4:27 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> Luke Kenneth Casson Leighton schreef op wo 23-09-2020 om 19:03 [+0100]:
> > staf says that with no clock timing constraint checking in coriolis2
> > it is unwise to try multiple clocks.  therefore no PLL and only
> > digital dividing of an incoming signal, 50mhz is perfectly reasonable.
> The PLL will be included but what we agreed upon is that only one
> power/clock domain is allowed on the prototype so no cross-domain
> problems can occur in the design.

ah ok - great!  yes that allows Dmitri to test what he is doing.

hmm hmm what should we do, then, if the PLL does not work?  i think it
might be a good idea to have an external pin that allows selection
between external digital clock and the PLL, what do you think?

> The JTAG wishbone interface has been
> specifically designed to be able to avoid possible problem if the speed
> if not too high compared to main CPU clock.

yes, it's critically important that it be independent.

staf could i ask you if you could have a quick look at this?


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