[Libre-soc-dev] change of tapeout date, and roadmap for 180nm ADIC

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Sep 23 19:03:56 BST 2020

i had a conference call today with staf, dmitri and jean-paul to
discuss the practical details of the 180nm ASIC.  staf will be putting
the agenda into the bugtracker later.  it was 3 hours, seriously long.

staf has had a lot more to do on the cell library than expected so we
are moving to 2 dec 2020.

jean-paul needs at least one month to do nothing but checking, so this
is 2 nov latest.

we have 2 weeks in which to solve thing like the litex issues and get
"a first version" (no new features as of today).  this will give jean
paul a stable base to work from.

this will include checking of longest path and to ensure setup time
and hold time on all FFs are ok.

in the intervening time the benefits of being able to boot linux i.e.
an MMU are such a leap that it is compelling to try.  also Staf would
like to try an SRAM block and dcache and icache is a way to do that.

so for a second iteration we have 5 weeks to try to get MMU in, test
JTAG, and staf can design a fixed size custom SRAM block.

if we cannot get the 2nd iteration working then we fall back to the 1st.

staf says that with no clock timing constraint checking in coriolis2
it is unwise to try multiple clocks.  therefore no PLL and only
digital dividing of an incoming signal, 50mhz is perfectly reasonable.

we also thought it may be worthwhile to do a 2nd 180nm or 130nm ASIC
middle of next year.  this one could have the PLL, and also there will
be interns working for Jean Paul on timing and buffers which will
improve speed and layout.

notes to go on bugtracker later.


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