[Libre-soc-dev] daily kan-ban update 20sep2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Sep 20 20:30:09 BST 2020
ok the ls180soc.py litex code works, as does the pinouts ls180.py and
i updated the coriolis2 PNR to use it. next thing there will be to
add a ring of IO pads.
however before handing over to jean-paul and staf there is the JTAG to add.
firstly using staf's c4m jtag, this will allow him to "scan" the IO
Pads and also i think interact directly with the wishbone bus so it
can do read and write.
it does not talk to the DMI interface though so cole and i are
converting microwatt DMI 2 JTAG FSM for that.
which runs smack into an asynchronous clock issue where of course JTAG
CLK is not only external it has absolutely nothing to do with the main
so i experimented successfully with a little bit of code that can do
ASYNC FF stabilisation in nmigen and got comfortable with it. it
needs 3 simulation processes: one at the main clock, one to *generate*
the external clock and one to do an async "trigger" at the rate of
that slower external clock.
with that done, tomorrow i can do a unit test for the dmi2jtag.py code
that uses the exact same principle. hopefully without having to write
too much in the way of JTAG testing infrastructure.
finally once the dmi2jtag.py code is done it can be linked into
ls180soc.py along with staf's jtag code and we are into testing and
finalising for the tapeout.
the soc is *not* going to have an onboard ROM. it will be run through
the JTAG interface by uploading into a small SRAM then executing that.
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