[Libre-soc-dev] big.little GPU PowerISA architectures
pangelo at void.io
Sat Sep 19 20:27:51 BST 2020
On Sat, 2020-09-19 at 11:41 +0100, Luke Kenneth Casson Leighton wrote:
> a fascinating idea came up on phoronix which suits a GPU architecture
> extremely well: subsets of PowerISA on "little" cores, with extremely
> wide Vector Processing, and tiny Instruction Caches, but otherwise
> full SMP. even some "scalar" (standard UNIX SMP) workloads would
> still then run on those cores, and if an instruction is encountered
> which they cannot cope with, the "illegal instruction" raised would
> have them context-switched to a "big" core where they would then
> successfully complete.
I think this has some precedent in the Cell Broadband Engine:
although the SPEs dis not use the PowerPC ISA, but a custom SIMD optimized one.
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