[Libre-soc-dev] daily kan-ban update 12sep2020

[Luke Kenneth Casson Leighton]

read and write to dcache seems to be "initially functional" (in
non-mmu mode), the very *very* basic dcache test does two loads (at
the same location), causing a read-miss the first time and a read-hit
the second.  a follow-up write at the same location also gets a "store
hit".

the dcache code itself... well, it's going to need conversion to use
Memory, because if it isn't converted then the tags etc. will pretty
much remain as flip-flops, not SRAM.

l.

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