[Libre-soc-dev] daily kan-ban update 08sep2020

whygee at f-cpu.org whygee at f-cpu.org
Tue Sep 8 20:33:42 BST 2020

On 2020-09-08 17:21, Luke Kenneth Casson Leighton wrote:
> therefore: rather than route 192+ wires across entire swathes of the
> chip (to 12 separate pipelines), all you do is *PARTIALLY* decode the
> instruction (enough to know which pipeline to deliver to), then route
> the *raw* instruction (only 32-bit) over to the pipeline, and have it
> *locally* decode *ONLY* the instruction fields that it actually needs.
> this does mean however that immediates get decoded more than once, for
> example.  given that it's local, i'm not concerned about that.  it's
> the number of wires crossing the chip that's got to come down.
> l.

it seems like a good move to me because this would also decrease power 
other things, through easier routing, lower capacitance load, ...

CDC6600s were hand-wired in 3D but our chips are limited to 2D (2.5D 
the metal layers). It made sense for a CDC6600 to have all the bits 
and taken directly to the units, because transistors were expensive.
Today, routing is a major bottleneck, particularly at that scale...


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