[Libre-soc-dev] Libre-SOC Versa ECP5 FPGA, Litex BIOS first boot

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Sep 4 00:17:26 BST 2020

On Thursday, September 3, 2020, Samuel Falvo II <sam.falvo at gmail.com> wrote:

> On Thu, Sep 3, 2020 at 12:44 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> > and multi-issue, yes.
> Sweet!  Congrats!!

oh, that's the future version.  right now it is a FSM, waits until all
hazards are clear before moving to the next instruction.

however it is pretty trivial to drop in an inorder hazard detector or a DM
set because all the "management" code is there, all those REQ and GO
signals, you remember we talked about 15 months ago?

i haven' put that in because it will take about 6 weeks and there isn't
time before October.

so the next main focus is to get interrupts integrated, and some
peripherals, and do the ASIC layout.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the Libre-soc-dev mailing list