[Libre-soc-dev] high performance

Jacob Lifshay programmerjake at gmail.com
Thu Oct 29 20:00:52 GMT 2020

On Thu, Oct 29, 2020, 12:40 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Thu, Oct 29, 2020 at 7:14 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:


of course it also means upping the register file port bandwidth and
> the operand forwarding buses, which is where it gets sliiightly tricky
> for increasing single-core performance.

who says we need the register file to be homogenous? we can just have the
first 32 integer registers be in a 8r4w or something, and the upper 96
registers can be 4r1w 4-way banked.
We could have the first 32 FP registers be 4r2w and the rest just like the
upper 96 integer regs.

> Maybe we could compete with the Intel Core 2 or Cortex A72 in
> > single-threaded tasks :)
> muhahah oosorry.

I was trying to resist the urge XD

> yeah i don't see why not.

Caches. Sad but true.


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