[Libre-soc-dev] WIP demo of deficiency of 6600-derived architecture compared to register renaming

Jacob Lifshay programmerjake at gmail.com
Wed Oct 28 03:24:52 GMT 2020

On Tue, Oct 27, 2020, 15:19 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On 10/27/20, Jacob Lifshay <programmerjake at gmail.com> wrote:
> > On Tue, Oct 27, 2020, 14:24 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >>
> >> 2) in column 3 i'm not seeing an INT reg write.  so the delay "Av r3"
> >> is unnecessary.
> >>
> >
> > That's caused by waiting for the associated memory read to finish before
> > writing the ldu's address register, otherwise a sigsegv could cause the
> > corruption of the register's previous value.
> ah true but only until the LDST is detected as being clear of the LDST
> hazard.  it would be perfectly reasonable to assume that the required
> data is in the L1 cache, and that TLB lookup after AGEN gives the "ok"
> straight away.
> i.e. you don't have the LDST Addr Shadow held until the last minute.
> wait... no, hang on, you've misunderstood Shadowing.

not really

  both the LDST
> *and* all following instructions (all of them) are shadowed by the
> so whilst the AGEN (update of ldu) write cannot go ahead, OpFWDing
> definitely can.

notice that's exactly what happens to instruction #17.m: the load result is
forwarded to instruction #18 on cycle 10.


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