[Libre-soc-dev] silicon catalyst starting in canada

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Oct 18 14:23:30 BST 2020

On Sun, Oct 18, 2020 at 1:42 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> Luke Kenneth Casson Leighton schreef op zo 18-10-2020 om 12:46 [+0100]:
> > explaining that to an investor is real simple and if they don't
> > understand that this is what the *customer* wants then we simply
> > politely end the conversation and move on to the next investor.
> Problem is that investors may say they understand it until they realize
> along the way they can't realize the ROI target.

here, we have to follow the lead on what STMicro, Texas Instruments
etc. do.  this is: to add in a pinmux and present multiple potential
market scenarios, such that the SoC can be reconfigured to 5 to 10
different products.

ST and ATMEL actually make the exact same die and sell it in 12 to 15
different packages!  what typically happens is that during testing the
e.g. USB port fails.  rather than chuck it out they go "oh dear let's
sell that one as the STM32F032 rather than the USB-enabled STM32F072".

typically however you need an investor who is specifically
knowledgeable about ASICs, or one that is prepared to entire into
"high risk, high reward".

> But this is only valid for the existing customer(s); for any new
> customer you will compete and your competitor likely does not have the
> same ROI requirements so may be able to live on lower margins.

interestingly they will be in the same boat as us.  they also have
that same "risk" that they have not made the SoC flexible enough to
cover multiple markets.

> I consider the RISC-V community still in their honeymoon period and
> time will tell if they will be able to mimic open source hardware
> development as Linux has done for OS development. For example I see
> possible conflict of interest between SiFive and the open source RISC-V
> Foundation.

yyeah, very much so.


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