[Libre-soc-dev] daily kan-ban update 15oct2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Oct 15 18:27:22 BST 2020

On Thu, Oct 15, 2020 at 2:39 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> am up to this commit, disabling litex interrupts (using polling) still
> works on Versa ECP5

ahh at frickin last.  it was the dummy PLL that i'd added, with clock
re-routing, not properly connected up.  gaah.  ok so we have "working
FPGA of current master" after i added a bypass mechanism of the PLL
when building verilog.


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