[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

Cole Poirier colepoirier at gmail.com
Wed Oct 14 20:55:06 BST 2020

On Wed, Oct 14, 2020 at 12:40 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On 10/14/20, Cole Poirier <colepoirier at gmail.com> wrote:
> > hopefully you get the gist of what I’m saying.
> i do.  the reason i am doing the bisect is to find at what point the
> FPGA upload stopped working.
> because we use git anyone including you can go back through the
> history.  plus, *before* you committed anything, i believe i said
> latest master is not working.

Right... thanks for jogging my memory, I remember that now about the
latest master not working on fpga 1-2 weeks ago. Indeed, doing any
serious engineering project without git is doomed from the start. This
is `git bisect` like we had to do a couple months back with nmigen?
I'll probably leave that to you and try to make some progress on the
list of things, esp JTAG, that we talked about yesterday.

> > ok the missing pieces are that litex doesn't understand XICS
> > interrupts, and they were in an unconfigured peripheral address
> > location anyway.
> > ```
> do try not to lose indentation, btw.  it looks like you wrote that
> because of no ">"s.

Oops, was afk on my phone, will do.

> > i.e. if we need litex to be able to understand XISC,
> not litex's problem / issue.  or it is, sort-of.
> interrupts are handled by a generic "signal" that gets allocated to
> litex peripherals on a per-bit basis.
> however just raising an interrupt means that, well, duh, the core will
> be interrupted.
> and if the software has not been written *to* deal with that
> interrupt, then guess what happens?
> so this is why it is and is not litex's problem

So, litex being the software that hasn't been written to deal with
these interrupts(?), needs to by modified to be able to handle
interrupts? Is this separate from, but related to the JTAG TAP pins
needing to be set up for both ulx3s and versa_ep5 fpga's?

> > and if not what our ‘workaround’/alternative is.
> try to run the microwatt xics.bin test in the fpga.

That's your plan for the workaround? or are you instructing me to do
this? I'll try it!


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