[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

Cole Poirier colepoirier at gmail.com
Wed Oct 14 19:53:17 BST 2020

On Wednesday, October 14, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Wed, Oct 14, 2020 at 6:56 PM Cole Poirier <colepoirier at gmail.com>
> wrote:
> > > Date:   Sat Sep 5 17:35:17 2020 +0100
>       ^^^^          ^^^^^^
> > Ok great, I thought it was from real code, not just me fiddling with
> > configuration params.
> that is real code: look at the date.

Yes awkward phrasing on my part, but that is indeed what I meant. That this
had occurred because of a substantive modification of code, very likely
done by you as you make up 99% of the project’s commits, not merely from my
very recent fiddling with configuration parameters. Was just looking to see
if it was my mistake so I could make a note of what I had done wrong. But
it’s almost as informative for me to learn from you correcting your own
mistakes. I feel like I’m not able to write clearly right now, but
hopefully you get the gist of what I’m saying.

> > Is it a hard limitation of litex that it can’t handles XICS style
> > interrupts,
> litex is software, therefore there is no limitation.

Great. I’m trying to understand what the implications of your earlier
comment on this thread were, so that I can better understand our code.

ok the missing pieces are that litex doesn't understand XICS
interrupts, and they were in an unconfigured peripheral address
location anyway.

i.e. if we need litex to be able to understand XISC, and if not what our
‘workaround’/alternative is.



More information about the Libre-soc-dev mailing list